A wide variety of devices exist at present currently referred to as a System-on-Chip (SoC), such a designation being often adopted to designate in general devices integrating several digital blocks. Such an SoC has a structure of the type shown in FIG. 1, namely a structure including a plurality of blocks M1, M2, . . . Mn acting as “master” blocks as well as a plurality of blocks S1, S2, . . . Sn acting as “slave” blocks. The blocks in question communicate through one or more buses. To simplify the description, just one bus—designated BUS1—will be considered in the following. However, all the remarks made both in respect of the prior art and in respect of the invention apply identically to arrangements including a plurality of buses.
The “master” blocks are generally intended to control the SoC by controlling the “slave” blocks. For instance, one master block (e.g. master block M1) can be a CPU, while slave blocks S1, S2, . . . , Sn are quite often represented by peripheral units such as display units, interfaces, etc. Operation of the SoC 10, is synchronized by a clock signal, generated by a clock generator 12 to be distributed to the various blocks as indicated by lines 14. Again, a plurality of such clock generators may be included in a single SoC. In the following only one clock generator 12 and the respective clock signal will be considered for the sake of simplicity.
Technological development, especially in respect of integration of CMOS transistors, leads to an increasing level of integration of digital devices. As a result of this, increasingly complex and sophisticated circuits (including entire digital systems) can be integrated to a single device in the form of a SoC. A factor militating against that tendency is the amount of power dissipated in the form of heat by the device. For that reason, solutions are needed which enable a judicious reduction of the power dissipated by the device.